Measuring memory bandwidth

Posted on 14 October, 2026

How Many Memory Channels Does an AMD EPYC 9005 Processor Really Need?

Introduction

When configuring a modern server, one of the most common questions customers ask is how many memory channels need to be populated. While it is widely understood that increasing the number of populated channels increases the theoretical memory bandwidth available to the processor, it is less clear whether every supported channel must be populated to achieve strong real-world performance.

This question has become particularly relevant with the introduction of processors that support different numbers of memory channels. For example, 5th Generation AMD EPYC processors support twelve DDR5 memory channels per socket, while Intel Xeon 6 is available in both eight- and twelve-channel variants. This naturally raises the question: does a twelve-channel processor need all twelve channels populated to remain competitive, or can it deliver comparable performance when configured with fewer DIMMs? With memory costs representing a significant part of a server configuration, particularly when DDR5 pricing is elevated, the answer also has direct implications for system cost.

To investigate, we compared an Intel Xeon 6761P with an AMD EPYC 9575F, each configured with eight 32 GB DDR5-6400 ECC RDIMMs. Intel Xeon 6 processors are available in two platform variants: Granite Rapids-SP, designed for mainstream enterprise and HPC deployments with up to eight DDR5 memory channels per socket, and Granite Rapids-AP, which integrates two compute dies into a single package and supports twelve DDR5 memory channels. This comparison focuses on the eight-channel Xeon 6761P and the twelve-channel AMD EPYC 9575F to evaluate how both platforms perform when configured with the same eight-DIMM DDR5-6400 memory configuration.

Intel Xeon 6761P populated with 8 memory DIMMs

In practice, the answer depends on the workload. Memory-intensive applications can benefit from additional memory channels, but many enterprise workloads—including virtualisation, web services, databases and general business applications—are not constrained by peak memory bandwidth once sufficient throughput is available. In these cases, populating every available memory channel may provide limited performance benefit while increasing the memory cost of the system.

AMD EPYC 9575F populated with 8 memory DIMMs

This distinction is becoming increasingly important as memory bandwidth receives greater attention in modern AI and high-performance computing platforms. As processors gain more cores and are increasingly paired with high-performance accelerators, ensuring sufficient data can be delivered to the compute resources has become an important platform design consideration. Recent processor roadmaps have therefore focused not only on increasing core counts, but also on increasing memory bandwidth through additional memory channels and faster DDR5 technologies.

This article examines whether an eight-DIMM configuration on a twelve-channel EPYC platform can deliver memory performance comparable to an eight-channel Xeon 6 system.

Understanding Memory Channels

Modern server processors contain multiple independent memory controllers, known as memory channels. Each populated DDR5 channel provides its own path between the processor and system memory. Adding additional channels increases the amount of data that can be transferred simultaneously.

For example, a processor configured with:

1 populated channel ? one data path
4 populated channels ? four parallel data paths
8 populated channels ? eight parallel data paths
12 populated channels ? twelve parallel data paths

More channels increase maximum theoretical memory bandwidth, but they do not automatically make every application faster. However, applications that continually stream large datasets through memory—such as scientific computing, computational fluid dynamics, modelling and some AI workloads—can utilise additional bandwidth effectively.

Many enterprise applications, however, are limited by processor execution, storage, networking or software efficiency rather than raw memory throughput.

Test Platform

To isolate memory performance, both systems were configured as similarly as possible.

Component	Intel Platform	AMD Platform
Processor	Intel Xeon 6761P	AMD EPYC 9575F
Sockets Installed	1	1
Memory Installed	8 x 32GB DDR5-6400 ECC RDIMM	8 x 32GB DDR5-6400 ECC RDIMM
Memory Channels Populated	8 of 8	8 of 12
Total Memory	256 GB (8 x 32 GB)	256 GB (8 x 32 GB)
Operating System	Ubuntu 24.04	Ubuntu 24.04

The two processors used in this comparison represent current-generation server platforms from Intel and AMD, each targeting high-performance single-socket deployments. The Intel Xeon 6761P is based on Intel’s Xeon 6 Performance-core (P-core) architecture and features 64 cores with support for eight DDR5 memory channels. The AMD EPYC 9575F is a 64-core processor from the EPYC 9005 family based on the Zen 5 architecture, supporting up to twelve DDR5 memory channels and offering higher peak memory bandwidth when fully populated.

Although the processors differ in architecture, memory controller design and cache layout, both systems were configured with a single 64-core CPU and eight identical DDR5-6400 DIMMs to provide a like-for-like comparison of memory subsystem performance.

Close up of the Boston 212H-TN server used for testing

In terms of software/BIOS, we set: a single NUMA domain (Intel SNC disabled, AMD NPS1), the Linux performance CPU frequency governor, and NUMA balancing disabled to ensure a consistent comparison.

Note, this configuration intentionally leaves four memory channels unpopulated on the EPYC platform. Since both systems are configured with the same eight DDR5-6400 memory channels, their theoretical peak memory bandwidth is identical. While architectural differences between the Intel Xeon 6761P and AMD EPYC 9575F may influence latency and memory controller efficiency, we would expect sustained memory bandwidth to be broadly comparable.

This is not an unusual or unsupported configuration. AMD’s recommended memory population guidelines include a number of balanced memory configurations that intentionally populate fewer than all twelve channels while maintaining symmetrical memory access across the processor. These configurations allow organisations to optimise memory capacity, cost and future upgrade flexibility without compromising memory subsystem balance.

Boston AS-2126HS-TN test platform, configured with a single AMD EPYC processor

Theoretical Memory Bandwidth

Before looking at the benchmark results, it is useful to understand the theoretical memory bandwidth available to each platform. This represents the maximum amount of data that can be transferred between the processor and memory under ideal conditions and provides a useful reference point when comparing measured performance.

Each DDR5-6400 memory channel provides a theoretical peak bandwidth of 51.2 GB/s, calculated from a transfer rate of 6,400 MT/s across a 64-bit (8-byte) memory interface.

Therefore:

Configuration	Theoretical Peak
8 channels	409.6 GB/s
12 channels	614.4 GB/s

While a fully populated twelve-channel EPYC processor offers substantially higher theoretical bandwidth, the key question is whether eight DDR5-6400 channels already provide sufficient memory throughput for many real-world workloads. The benchmarks in the following sections investigate how closely measured memory performance approaches these theoretical limits, and whether the additional bandwidth translates into improved application performance.

STREAM Memory Bandwidth Results

STREAM is one of the most widely used industry-standard benchmarks for measuring sustainable memory bandwidth. Rather than reporting theoretical peak performance, STREAM measures how quickly a processor can read from and write to main memory using simple vector operations that are representative of many memory-intensive scientific and engineering workloads. As a result, it provides a practical indication of the memory bandwidth that real applications can achieve.

To measure sustained memory bandwidth, we used the STREAM benchmark under Ubuntu 24.04.

STREAM Benchmark:	Intel Xeon 6761P	AMD EPYC 9575F
Copy	321.6 GB/s	328.4 GB/s
Scale	320.8 GB/s	328.3 GB/s
Add	325.4 GB/s	332.4 GB/s
Triad	326.7 GB/s	332.3 GB/s

Intel Xeon 6761P vs AMD EPYC 9575F – 8 × 32 GB DDR5-6400 ECC RDIMM

The STREAM results show both platforms delivering strong sustained memory bandwidth, with the AMD EPYC 9575F achieving comparable or marginally higher STREAM performance despite using only eight of its twelve available memory channels.

STREAM measures sustained memory throughput under a practical workload, rather than peak interface bandwidth. Achieving approximately 320–330 GB/s represents around 80% of the theoretical maximum, which is typical for sustained memory workloads and demonstrates that both platforms are effectively utilising their available memory bandwidth.

Intel Memory Latency Checker (MLC)

To complement the STREAM benchmark, we also evaluated both systems using Intel Memory Latency Checker (MLC). Although developed by Intel, MLC can also be used to measure memory bandwidth and latency on AMD platforms, making it a useful cross-platform comparison tool.

Unlike STREAM, which measures sustained application-level throughput, MLC places greater emphasis on the performance of the memory subsystem itself. It reports peak bandwidth under a range of read/write traffic patterns, helping to characterise the maximum performance available from the installed memory configuration.

The MLC results are summarised below. Across the mixed read/write workloads, both processors continued to produce closely matched results, demonstrating that an EPYC 9005 processor configured with eight memory channels can utilise the available bandwidth just as effectively as an eight-channel Xeon 6 platform.

MLC Test:	Intel Xeon 6761P	AMD EPYC 9575F
Idle latency	124.2 ns	112.8 ns
Peak read bandwidth	383.2 GB/s	383.7 GB/s
3:1 Read	337.9 GB/s	335.7 GB/s
2:1 Read	328.6 GB/s	329.5 GB/s
1:1 Read	311.9 GB/s	316.5 GB/s
STREAM Triad-like	328.0 GB/s	331.7 GB/s
Non-temporal writes	325.5 GB/s	323.2 GB/s

Intel Xeon 6761P vs AMD EPYC 9575F – 8 × 32 GB DDR5-6400 ECC RDIMM

Taken together, the STREAM and MLC results show that both platforms make highly effective use of an identical eight-channel DDR5-6400 memory configuration. Across all tests, the AMD EPYC 9575F delivered memory performance that closely matched, and in some cases marginally exceeded, the Intel Xeon 6761P despite using only eight of its twelve available memory channels.

STREAM demonstrated that both systems sustained approximately 80% of their theoretical memory bandwidth during practical workloads, while MLC showed that peak bandwidth exceeded 93% of the theoretical maximum under synthetic memory traffic. These results demonstrate that, when configured with eight DDR5-6400 DIMMs, the EPYC 9005 platform can utilise the available memory subsystem just as effectively as an equivalent eight-channel Xeon 6 system.

Having established that both platforms deliver comparable memory performance with an identical memory configuration, we next examine whether populating all twelve memory channels on the EPYC processor provides any measurable improvement in CPU-bound application performance.

Does Using Eight DIMMs Reduce CPU Performance?

The previous sections showed that an AMD EPYC 9575F configured with eight DDR5-6400 DIMMs delivers memory performance comparable to an eight-channel Intel Xeon 6761P. However, because the EPYC processor supports twelve memory channels, we can also try to answer another question: does populating all twelve channels provide any measurable improvement in CPU-bound application performance?

To answer this, we increased the EPYC memory configuration from eight to twelve DDR5-6400 DIMMs and repeated a selection of memory and CPU benchmarks. This allows us to quantify both the increase in available memory bandwidth and its impact on real-world application performance. Before evaluating CPU performance, we confirmed that populating the additional four DIMMs increased available memory bandwidth as expected.

To do this, Intel Memory Latency Checker (MLC) was used, this time to evaluate the effect of increasing the memory configuration. As expected, the additional memory channels substantially increased the available memory bandwidth while leaving memory latency virtually unchanged.

Measuring memory bandwidth on 5th Generation AMD EPYC and Intel Xeon 6 - Boston Limited

Memory Performance with 12 DIMMs

Intel Memory Latency Checker

To quantify the benefit of populating all twelve memory channels, we repeated the Intel Memory Latency Checker (MLC) benchmark after increasing the memory configuration from eight to twelve DDR5-6400 DIMMs. This allows us to isolate the effect of additional memory channels while keeping the processor, memory speed and all other system components unchanged.

Metric	8 DIMMs	12 DIMMs
Idle Latency	112.8 ns	113.4 ns
Peak Read Bandwidth	383.7 GB/s	560.0 GB/s
1:1 Read:Write	316.5 GB/s	472.5 GB/s
STREAM Triad-like	331.7 GB/s	500.1 GB/s

AMD EPYC 9575F – 8 × 32 GB DDR5-6400 vs 12 × 32 GB DDR5-6400

As expected, populating all twelve memory channels significantly increased the available memory bandwidth. Peak read bandwidth increased by almost 46%, while the mixed read/write and STREAM Triad-like workloads improved by approximately 50%. Memory latency remained virtually unchanged, demonstrating that the additional DIMMs primarily increase bandwidth rather than reducing access latency.

These results closely align with the increase in theoretical bandwidth available from twelve DDR5-6400 memory channels, confirming that the additional memory channels are being effectively utilised by the EPYC memory subsystem.

Real-World CFD Performance

The increase in memory bandwidth measured by MLC is useful, but synthetic bandwidth measurements do not necessarily translate directly into application performance. To determine whether the additional memory channels provide a measurable benefit in a real workload, we also compared OpenFOAM performance using eight and twelve DDR5-6400 DIMMs.

We used the drivaerFastback benchmark with the Medium Mesh Size, running the same OpenFOAM workload on the EPYC 9575F processor. The only change between the two configurations was the number of populated memory channels.

Configuration	8 DIMMs	12 DIMMs
Mesh Time	96.67 s	92.38 s
Execution Time	334.26 s	268.32 s

The additional memory channels had a relatively small effect on mesh generation, reducing mesh time by approximately 4.4%. The difference during the main CFD execution, however, was considerably larger. Execution time fell from 334.26 seconds with eight DIMMs to 268.32 seconds with twelve DIMMs, representing a 19.7% reduction in runtime and demonstrating a substantial performance improvement from the additional memory channels.

This demonstrates that the additional memory bandwidth available from populating all twelve memory channels can translate into a substantial improvement in real-world application performance. Although the EPYC 9575F processor itself is unchanged, the memory configuration can therefore have a significant effect on the performance of bandwidth-sensitive workloads such as CFD.

The result also puts the MLC measurements into practical context: the additional memory channels are not simply increasing a synthetic bandwidth score but can provide a measurable performance advantage in a demanding engineering workload.

CPU Benchmark Results – 8 vs 12 Channels

With the increase in available memory bandwidth confirmed, we evaluated whether this translated into higher application performance using a range of CPU-focused benchmarks representative of software development, rendering, compression and cryptographic workloads.

Benchmark	8 DIMMs	12 DIMMs
Timed Linux Kernel Compilation	27.442 s	27.676 s
C-Ray 2.0 (5K)	59.343 s	59.861 s
7-Zip Compression	683,640 MIPS	707,879 MIPS
7-Zip Decompression	491,167 MIPS	443,930 MIPS
OpenSSL RSA4096 Verify	1,585,651 verify/s	1,569,438 verify/s
OpenSSL SHA512	42.99 GB/s	42.83 GB/s
OpenSSL AES-256-GCM	925.89 GB/s	919.46 GB/s
OpenSSL ChaCha20-Poly1305	496.47 GB/s	490.84 GB/s

AMD EPYC 9575F – 8 × 32 GB DDR5-6400 vs 12 × 32 GB DDR5-6400

Increasing the available memory bandwidth by approximately 50% resulted in less than 1% variation across the majority of CPU-focused benchmarks. Linux kernel compilation, C-Ray and the OpenSSL workloads all delivered almost identical results between the two configurations, with differences well within the level of variation typically observed between repeated benchmark runs. The only notable exception was the 7-Zip decompression test, which produced a lower score with twelve DIMMs. As this behaviour was not reflected elsewhere in the benchmark suite, it appears to be specific to this workload rather than representative of overall processor performance.

These results demonstrate that fully populating all twelve memory channels on a 5th Generation AMD EPYC processor does not automatically improve application performance. While memory bandwidth increased by approximately 50%, CPU-bound workloads showed little measurable benefit from the additional channels.

Performance, Cost and Memory Configuration

The additional memory bandwidth provided by twelve populated channels comes at an additional memory cost. With DDR5 memory prices currently elevated, the cost of populating every available memory channel is an increasingly important consideration when configuring a server.

The results so far show that the additional bandwidth does not automatically translate into higher application performance. For many CPU-focused workloads, eight DIMMs delivered performance very close to the twelve-DIMM configuration despite the substantially higher bandwidth available from twelve channels.

This creates an opportunity to optimise memory configuration according to the workload. Where an application does not require the additional memory bandwidth, populating fewer channels can reduce the cost of the system while maintaining comparable application performance. This can be particularly relevant where the required memory capacity can already be achieved using fewer, higher-capacity DIMMs.

Conversely, workloads that can make effective use of additional memory bandwidth may justify the additional cost of populating all twelve channels. The OpenFOAM results in the following section provide an example of this, demonstrating a substantial reduction in execution time when moving from eight to twelve DIMMs.

The optimal memory configuration is therefore not necessarily the one with every channel populated. Instead, memory capacity, bandwidth requirements, workload characteristics and system cost should all be considered when selecting the appropriate configuration.

Conclusions

One of the key findings from this investigation is that the number of memory channels supported by a processor should not be confused with the number that must be populated to achieve strong real-world performance.

Further testing on the EPYC platform showed that increasing from eight to twelve DDR5-6400 DIMMs increased available memory bandwidth by approximately 50% yet produced little measurable improvement across a range of CPU-bound application benchmarks.

For organisations balancing cost, capacity and performance, this provides greater flexibility when configuring single-socket EPYC platforms. Rather than assuming all twelve memory channels must always be populated, memory can be sized to match the workload while still delivering excellent performance for many enterprise applications. Where the required memory capacity can be achieved with fewer DIMMs, this can also reduce system cost without sacrificing meaningful application performance.

For workloads that are highly memory bandwidth constrained, populating additional channels remains the path to achieving the maximum available bandwidth from the EPYC platform. However, for many general enterprise, virtualisation, and compute workloads, an eight-DIMM configuration can provide an excellent balance of performance, capacity and cost.

Looking ahead, memory bandwidth will continue to increase across future server platforms through faster DDR5 technologies such as 8000 MT/s RDIMMs which Intel announced support for, and next-generation MRDIMMs. These developments are driven by increasingly data-intensive workloads, particularly AI, analytics and HPC, where keeping CPUs and accelerators supplied with data is becoming just as important as raw compute capability. However, our results also demonstrate that for many current enterprise workloads, balanced memory population remains more important than simply populating every available channel.

About Boston

At Boston, we work closely with customers to evaluate the latest server technologies and help identify the right platform for each workload. Whether you’re deploying virtualisation infrastructure, HPC clusters, AI environments or enterprise applications, our engineering team can benchmark and validate configurations to ensure you achieve the best balance of performance, capacity and cost.

As this testing demonstrates, server configuration is about more than simply selecting the processor with the highest specification. Memory population, CPU architecture and workload characteristics all influence real-world performance, and our team regularly performs independent testing to help customers make informed deployment decisions.

In addition to the platforms featured in this article, Boston offers a comprehensive portfolio of AMD EPYC and Intel Xeon servers, as well as fully bespoke systems designed and validated for your specific applications and infrastructure requirements.

Boston Labs also enables customers to evaluate the latest hardware, software and infrastructure technologies before deployment. If you would like to discuss your workload, compare server platforms or arrange benchmark testing, please contact our team at [email protected] or call +44 (0)1727 876100. Our experienced solution architects will be happy to help you identify the best platform for your environment.